The invention relates to a nonvolatile semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device, which is suitable to speed up an erase operation and a read operation and improve data retention characteristics, write/erase endurance characteristics, or write disturb characteristics.
As electrically erasable and programmable nonvolatile semiconductor memory devices, EEPROMs (Electrically Erasable and Programmable Read Only Memories) are popularly used. Each of these memory devices (memories) represented by flash memories has a conductive floating gate electrode or a trapping insulator film which are surrounded by an oxide film under a gate electrode of a MOS (Metal Oxide Semiconductor) transistor. This trapping insulator film means an insulator film, which can accumulate charges therein, and may be, by way of example, a silicon nitride film or the like.
Injection and discharge of charges into/from these charge accumulation regions cause the threshold voltage of a MOS transistor to be shifted and to operate as a memory device.
There is used, as the flash memory, a split-gate cell employing a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure that will be described later.
In the memory, since a silicon nitride film is used as a charge accumulation region, the following advantages are achieved: in comparison with a conductive floating gate film, 1) reliability of data retention is high due to discrete accumulation of charges; 2) because of high reliability of the data retention, oxide films located on upper and/or lower side of the silicon nitride film can be thinned and write/erase operations can be performed at low voltages; and the like.
By using the split-gate cell, the following advantages are also achieved: 1) hot electrons can be injected into the silicon nitride film by a source-side injection method and good electron injection efficiency can be achieved, whereby the write operation can be performed at a high speed and with a low current; 2) since the write/erase operations are easily controlled, a peripheral circuit can be made small in scale; and the like.
As erase methods for the above-mentioned memory, there are given two methods, i.e., a tunneling erase method and a BTBT (Band-To-Band Tunneling) hot hole injection erase method.
For example, Patent Document 1 (Japanese Patent Laid-open No. 2001-102466) discloses a memory cell using a tunneling erase method. Further, Patent Document 2 (U.S. Pat. No. 5,969,383) discloses a memory cell using the BTBT hot hole injection erase method.
In the tunneling erase method, electrons, injected into a silicon nitride film by a source-side injection write method, are tunneled through an oxide film located on upper or lower side of the silicon nitride film by applying a positive or negative voltage to a gate electrode, and are extracted into the gate electrode or a substrate to perform an erase operation.
In the other BTBT hot hole injection erase method, a high voltage is applied between a source and a gate electrode, and holes with positive charges generated by the BTBT are accelerated by an electric field directed to a channel direction at an end of a source diffusion layer and are attracted by the negative voltage of the gate electrode and are injected into the silicon nitride film to perform an erase operation (see FIG. 32).
[Patent Document 1]
Japanese Patent Laid-open No. 2001-102466
[Patent Document 2]
U.S. Pat. No. 5,969,383